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INTEGRATED CIRCUITS
PCK2022RA CK00 (100/133 MHz) spread spectrum differential system clock generator
Product data 2001 Jun 12
Philips Semiconductors
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
FEATURES
* 3.3 V operation * Eight differential CPU clock pairs * One IO clock at 33 MHz and 66 MHz * Two 48 MHz clocks at 3.3 V * One 14.318 MHz reference clock * Power management control pins * Host clock jitter less than 200 ps cycle-to-cycle * Host clock skew less than 150 ps pin-to-pin * Spread Spectrum capability * Optimized frequency and spread spectrum performance
DESCRIPTION
This part replaces PCK2022R with improved frequency and spread spectrum performance. The PCK2022RA is a clock synthesizer/driver for a Pentium IIITM and other similar processors. The PCK2022RA has eight differential pair CPU current source outputs, one 33/66 MHz output which is configurable on power-up, two 48 MHz clocks which can be disabled on power-up, and one 3.3 V reference clock at 14.318 MHz which can also be disabled on power-up. All clock outputs meet Intel's drive strength, rise/fall times, jitter, accuracy, and skew requirements. The part possesses a dedicated power-down input pin for power management control. This input is synchronized on chip, and ensures glitch-free output transitions. In addition, the part can be configured to disable the 48 MHz outputs for lower power operation and an increase in the performance of the functioning outputs. The IOCLK and REFCLK can also be disabled for the highest performance of the Host outputs.
PIN CONFIGURATION
IOCLK VDD 48M_0/SELA 48M_1/SELB VSS VDD HCLK0 HCLKB0 VSS 1 2 3 4 5 6 7 8 9 48 SEL100/133 47 VSS 46 VDDA 45 VSSA 44 PWRDWN 43 VDD 42 HCLK4 41 HCLKB4 40 VSS 39 HCLK5 38 HCLKB5 37 VDD 36 HCLK6 35 HCLKB6 34 VSS 33 HCLK7 32 HCLKB7 31 VDD 30 MULTSEL0 29 MULTSEL1 28 VSS 27 VSSA 26 IREF 25 VDDA
HCLK1 10 HCLKB1 11 VDD 12
HCLK2 13 HCLKB2 14 VSS 15 HCLK3 16 HCLKB3 17 VDD 18 REFCLK/SELC 19 SPREAD 20 VSS 21 XIN 22 XOUT 23 VDD 24
SW00665
ORDERING INFORMATION
PACKAGES 48-Pin Plastic TSSOP TEMPERATURE RANGE 0 to +70 C ORDER CODE PCK2022RADGG DRAWING NUMBER SOT362-1
Intel and Pentium III are trademarks of Intel Corporation.
2001 Jun 12
2
853-2257 26484
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
PIN DESCRIPTION
PIN(S) 1 3, 4 7, 8 10, 11 13, 14 16, 17 42, 21 39, 38 36, 35 33, 32 19 20 21 22 26 29, 30 44 48 2, 6, 12, 18, 24, 31, 37, 43 5, 9, 15, 21, 28, 34, 40, 47 25, 46 27, 45 SYMBOL IOCLK 48M_0/SELA 48M_1/SELB HCLK0 HCLKB0 HCLK1 HCLKB1 HCLK2 HCLKB2 HCLK3 HCLKB3 HCLK4 HCLKB4 HCLK5 HCLKB5 HCLK6 HCLKB6 HCLK7 HCLKB7 REFCLK/SELC SPREAD XIN XOUT IREF MULTSEL0 MULTSEL1 PWRDWN SEL100/133 VDD3 FUNCTION Dual frequency pin which can operate at either 33 MHz or 66 MHz per the selection table. 3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in. Host output pair 0 Host output pair 1 Host output pair 2 Host output pair 3 Host output pair 4 Host output pair 5 Host output pair 6 Host output pair 7 3.3 V fixed 14.318 MHz output. During power-up, pin functions as a latched input that enables SELC prior to the pin being used for the clock output. Part must be clocked to latch data in. Enables spread spectrum mode when held LOW on differential host outputs and 33 MHz IOCLK clocks. Asserts LOW. Crystal input Crystal output This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to ground in order to establish the correct current. Select input pin used to control the scaling of the HCLK and HCLKB output current. Device enters power-down mode when held LOW. Asserts LOW. Select input pin for enabling 133 MHz or 100 MHz CPU outputs 3.3 V power supply
GND
Ground
AVDD AGND
3.3 V power supply for analog circuits Ground for analog circuits
2001 Jun 12
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Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
BLOCK DIAGRAM
PWRDWN XIN 14.318 MHz OSC USB PLL PWRDWN SELA/B PWRDWN SELC
REF[0] (14.318 MHz)
XOUT
48MHz[0..1] (3 V)
HOST[0..7] (100/133 MHz)
IREF
IBIAS
PWRDWN SYS PLL
HOST_BAR[0..7] (100/133 MHz)
PWRDWN
IOCLK (33/66 MHz)
PWRDWN SEL100/133 LOGIC SPREAD MULTSEL0 MULTSEL1
SW00666
FUNCTION TABLE
SEL100/133 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SELA 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SELB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SELC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HOST 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz Low 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz 200 MHz 133 MHz TCLK/2 133 MHz 48MHz 48 MHz 48 MHz Hi-Z Hi-Z Hi-Z 48 48 MHz1 MHz1 Hi-Z 48 MHz 48 MHz Hi-Z Hi-Z 48 MHz 48 MHz1 TCLK/4 48 MHz1 IOCLK 33.3 MHz 66.7 MHz 33.3 MHz 66.7 MHz Low 33.3 MHz Hi-Z 66.7 MHz 33.3 MHz 66.7 MHz 33.3 MHz 66.7 MHz 33.3 MHz 33.3 MHz TCLK/4 66.7 MHz REFCLK 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz Low 14.318 MHz Hi-Z 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz TCLK 14.318 MHz
NOTE: 1. These frequencies are for debug, and thus can vary a small amount from the values listed at the vendor's discretion.
2001 Jun 12
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Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
Table 1. Host swing select functions
MULTSEL0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BOARD IMPEDANCE 60 50 60 50 60 50 60 50 30 25 30 25 30 25 30 25 IREF RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 475 1% IREF = 2.32 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA RREF = 221 1% IREF = 5 mA IOH IOH = 5*IREF IOH = 5*IREF IOH = 6*IREF IOH = 6*IREF IOH = 4*IREF IOH = 4*IREF IOH = 7*IREF IOH = 7*IREF IOH = 5*IREF IOH = 5*IREF IOH = 6*IREF IOH = 6*IREF IOH = 4*IREF IOH = 4*IREF IOH = 7*IREF IOH = 7*IREF VOH @ IREF = 2.32 mA 0.71 V 0.59 V 0.85 V 0.71 V 0.56 V 0.47 V 0.99 V 0.82 V 0.75 V 0.62 V 0.90 V 0.75 V 0.60 V 0.50 V 1.05 V 0.84 V
NOTE: The outputs are optimized for the configurations shown shaded. CONDITIONS IOUT IOUT VDD = 3.3 V VDD = 3.3 V 5% CONFIGURATION All combinations; see Table 1 above All combinations; see Table 1 above LOAD Nominal test load for given configuration Nominal test load for given configuration MIN. -7% of IOH see Table 1 above -12% of IOH see Table 1 above MAX. +7% of IOH see Table 1 above +12% of IOH see Table 1 above
POWER-DOWN MODE
PWRDWN Asserts LOW 0 = Active HCLK/HCLKB Host = 2*IREF Host_bar = undriven IOCLK LOW 48MHz LOW REFCLK LOW
NOTE: The differential outputs should have a voltage forced across them when power-down is asserted.
SPREAD SPECTRUM FUNCTION
SPREAD # 1 0 FUNCTION Host/IOCLK No Spread Host/IOCLK Down spread -0.5% 5 48 MHz PLL REFCLK No Spread No Spread
2001 Jun 12
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
ABSOLUTE MAXIMUM RATINGS
SYMBOL VDD3 IIK VI IOK VO IO Tstg Ptot PARAMETER DC 3.3 V supply DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current Storage temperature range Power dissipation per package plastic medium-shrink (SSOP) For temperature range -40C to +125C; above +55C derate linearly with 11.3 mW/K VI < 0 Note 2 VO > VDD or VO < 0 Note 2 VO = 0 to VDD CONDITIONS LIMITS MIN -0.5 -- -0.5 -- -0.5 -- -65 -- MAX 4.6 -50 VDD 50 VDD+0.5 50 +150 850 UNIT V mA V mA V mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under "recommended operating condition" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage rating may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VDD3 AVDD CL PARAMETER DC 3.3 V supply voltage DC 3.3 V analog supply voltage Capacitive load on: IOCLK 48 MHz clock REF Reference frequency, oscillator normal value Operating ambient temperature range in free air Must meet IOCLK 2.1 requirements 1 device load 1 device load CONDITIONS LIMITS MIN 3.135 3.135 10 10 10 14.31818 0 MAX 3.465 3.465 30 20 20 14.31818 +70 UNIT V V pF pF pF MHz C
fref Tamb
POWER MANAGEMENT
CONDITION MAXIMUM 3.3 V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAPACITANCE LOADS VDDL = 3.465 V ALL STATIC INPUTS = VDD3 OR VSS 60 mA 250 mA
Power-down mode (PWRDWN = 0) Full active 100/133 MHz
2001 Jun 12
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Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
DC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70 C SYMBOL VIH VIL VOH3 VOL3 VOHP VOLP IO OH IO OH IO OH IO OL IO OL VO OL II IOZ Cin Cout Cxtal PARAMETER HIGH level input voltage LOW level input voltage 3.3 V output HIGH voltage REF, 48M 3.3 V output LOW voltage REF, 48M 3.3 V output HIGH voltage IOCLK 3.3 V output LOW voltage IOCLK Output HIGH current IOCLK Output HIGH current 48 MHz, REF Output HIGH current HOST/HOST_BAR Output LOW current IOCLK Output LOW current 48 MHz, REF HOST/HOST_BAR HOST/HOST BAR Input leakage current 3-State output OFF-State current Input pin capacitance Output pin capacitance Crystal input capacitance CONDITIONS VDD (V) 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 3.465 3.135 3.465 3.135 3.465 3 135 to 3 465 3.135 3.465 3.135 3.465 VSS = 0 V 3.465 3.465 IOH = -1 mA IOH = 1 mA IOH = -1 mA IOH = 1 mA VOUT = 1.0 V VOUT = 3.135 V VOUT = 1.0 V VOUT = 3.135 V 0.66 V 0.76 V VOUT = 1.95 V VOUT = 0.4 V VOUT = 1.95 V VOUT = 0.4 V RS = 33.2 RP = 49.9 0 < VIN < VDD3 VOUT = VDD or GND IO = 0 Type 5 y 12 - 55 Type 3 y 20 - 60 Type X1 Type 5 y 12 - 55 Type 3 y 20 - 60 Type X1 OTHER MIN 2.0 VSS-0.3 2.0 -- 2.4 -- -33 -- -29 -- 11 -- 30 -- 29 -- -- -50 -- -- -- 13.5 LIMITS TYP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX VDD+0.3 0.8 -- 0.4 -- 0.55 -- -33 -- -23 -- 12.7 -- 38 -- 27 0.05 0 05 50 10 5 6 22.5 UNIT V V V V V V mA mA mA mA mA mA mA mA mA mA V A A pF pF pF
2001 Jun 12
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Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
AC ELECTRICAL CHARACTERISTICS
VDD3 = 3.3 V 5%; fcrystal = 14.31818 MHz
Host clock outputs
Tamb = 0 to +70 C; see Figure 1 for waveforms and Figure 6 for test setup. LIMITS SYMBOL tPKP Abs Min Period tRISE tFALL tJITTER DUTY CYCLE tSKEW Rise/Fall Matching Vcrossover REFER TO NOTES ON PAGE 9. PARAMETER HOST CLK average period Absolute minimum host clock period HOST CLK rise time HOST CLK fall time HOST_CLK cycle-to-cycle jitter Output duty cycle HOST CLK pin-to-pin skew Rise and Fall time matching 133 MHz MODE MIN 7.5 7.35 175 175 -- 45 -- -- 40% VOH MAX 7.65 N/A 700 700 150 55 150 20% 55% VOH 100 MHz MODE MIN 10.0 9.85 175 175 -- 45 -- -- 40% VOH MAX 10.2 N/A 700 700 150 55 150 20% 55% VOH V ns ns ns ps ps % ps 11, 14, 20 11, 14, 20 11, 15, 20 11, 15, 20 11, 12, 14, 20 11, 14, 20 11, 14, 20 11, 16, 20 11, 14, 20 UNITS NOTES
IOCLK outputs
Tamb = 0 to +70 C LIMITS SYMBOL tPKP tPKH tPKL tRISE tFALL tJITTER DUTY CYCLE IOCLK period IOCLK HIGH time IOCLK LOW time IOCLK rise time IOCLK fall time Cycle-to-cycle jitter Output duty cycle PARAMETER 33 MHz MODE MIN 30.0 12.0 12.0 0.5 0.5 -- 45 MAX N/A N/A N/A 2.0 2.0 200 55 66 MHz MODE MIN 15.0 6.0 6.0 0.5 0.5 -- 45 MAX N/A N/A N/A 2.0 2.0 200 55 ns ns ns ns ns ps % 2, 3, 9, 20 5, 10, 20 6, 10, 20 8, 20 8, 20 18, 20 18, 20 UNITS NOTES
REFER TO NOTES ON PAGE 9.
USB clock output, 48MHz
Tamb = 0 to +70 C; lump capacitance test load = 20 pF LIMITS SYMBOL f fD tHKL tRISE tFALL tJITTER DUTY CYCLE Frequency, actual Deviation from 48 MHz 3V48MHZCLK LOW time 3V48MHZCLK rise time 3V48MHZCLK fall time Cycle-to-cycle jitter Output duty cycle 5.05 1.0 1.0 -- 45 PARAMETER 48 MHz MODE MIN 48.08 +167 N/A 4.0 4.0 250 55 MAX MHz ppm ns ns ns ps % 4 4 20 8, 20 8, 20 18, 20 18, 20 UNITS NOTES
REFER TO NOTES ON PAGE 9.
2001 Jun 12
8
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
REF clock output
Tamb = 0 to +70 C; lump capacitance test load = 20 pF LIMITS SYMBOL f tHKL tHKH tJITTER DUTY CYCLE Frequency, actual REFCLK LOW time REFCLK HIGH time Cycle-to-cycle jitter Output duty cycle 30 30 -- 45 PARAMETER 48 MHz MODE MIN 14.318 37 37 300 55 MAX MHz ns ns ps % 17, 20 20 20 18, 20 18, 20 UNITS NOTES
REFER TO NOTES ON PAGE 9.
All outputs
Tamb = 0 to +70 C LIMITS SYMBOL tPZL, tPZH tPZL, tPZH tSTABLE PARAMETER Output enable delay (all outputs) Output disable delay (all outputs) All clock stabilization from power-up 133 MHz MODE MIN 1.0 1.0 -- MAX 10.0 10.0 3 100 MHz MODE MIN 1.0 1.0 -- MAX 10.0 10.0 3 ns ns ms 20 20 7, 20 UNITS NOTES
REFER TO NOTES ON PAGE 9.
Group offset limits
GROUP Host to IOCLK OFFSET 1.5 - 3.5 ns Host leads MEASUREMENT LOADS (LUMPED) IOCLK @ 30 pF MEASUREMENT POINTS Host @ Cross point IOCLK @ 1.5 V NOTES 19, 20
NOTES TO THE AC TABLES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks. 3. The IOCLK clock is the Host clock divided by 4 in 33 MHz mode and divided by 2 in 66 MHz mode at Host = 133 MHz. IOCLK clock is the Host clock divided by 3 in 33 MHz and divided by 2/3 in 66 MHz mode at Host = 100 MHz. 4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default. 5. tHKH is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7. 6. tHKL is measured at 0.4 V for all outputs as shown in Figure 7. 7. the time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 8. tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 9. The average period over any 1 s period of time must be greater than the minimum specified period. 10. Calculated at minimum edge rate (1 V/ns) to guarantee 45-55% duty cycle. Pulse width is required to be wider at faster edge rate to ensure duty specification is met. 11. Test load is RS = 33.2 , RP = 49.9 . 12. Must be guaranteed in a realistic system environment. 13. Configured for VOH = 0.71 V in a 50 environment. 14. Measured at crossing points. 15. Measured at 20% to 80%. 16. Determined as a fraction of 2*(tRP - tRN) / (tRP + tRN), where tRP is a rising edge, and tRN is an intersecting falling edge. 17. Frequency generated by crystal oscillator 18. Voltage measure point (VM = 1.5 V). VDD = 3.3 V. 19. All offsets are to be measured at rising edges. 20. Parameters are guaranteed by design.
2001 Jun 12
9
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
AC WAVEFORMS
VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH - 0.3 V VOL and VOH are the typical output voltage drop that occur with the output load.
VOH HOST CLK 50% 50% VSS VI SEL1, SEL0 GND VOH HOST_BAR CLK 50% VSS tSKEW tPERIOD VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VOH COMPONENT MEASUREMENT POINTS VOH = 2.4 V OUTPUT HIGH-to-OFF OFF-to-HIGH VSS outputs enabled VY VM tPZH VM VX tPLZ tPZL VM
SW00667
Figure 1. HOST CLOCK
VDDL VIH = 2.0 V 1.5 V VIL = 0.7 V SYSTEM MEASUREMENT POINTS
VOL = 0.4 V VSS
outputs disabled
outputs enabled
SW00662
Figure 3. State enable and disable times
SW00668
Figure 2. 3.3 V clock waveforms
VDD
S1
2 VDD Open VSS 500
VI PULSE GENERATOR DUT
VO
RT
CL
500
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2 VDD VSS
VDD = VDDL or VDD3, depending on the output.
SW00660
Figure 4. Load circuitry for switching times
2001 Jun 12
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Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
PWRDWN
HOST CLK (INTERNAL)
PCICLK (INTERNAL)
PWRDWN
HOST CLK (EXTERNAL) PCICLK (EXTERNAL)
OSC & VCO
USB (48 MHz)
Figure 5. Power management
VDD CL HOST CRYSTAL 14.318 MHz DUT RS RP = 50
RS = 33.2
HOST_BAR RS CL RP = 50
Figure 6. HOST CLOCK measurements
tPKP DUTY CYCLE tPKH 3.3V CLOCKING INTERFACE 2.4 V 1.5 V 0.4 V tPKL tRISE tFALL
SW00659
Figure 7. 3.3 V clock waveforms
2001 Jun 12
11
A A A A
SW00669
SW00671
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
2001 Jun 12
12
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
NOTES
2001 Jun 12
13
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential system clock generator
PCK2022RA
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Date of release: 06-01 Document order number: 9397 750 08473
Philips Semiconductors
2001 Jun 12 14

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